Integrated circuit semiconductor memories must, of necessity, operate with a high degree of reliability in order to be used in computer related applications. The production of errors on even infrequent occasions can cause serious problems in computer controlled operations and data processing. The nature of MOSFET (metal-oxidesemiconductor field-effect transistor) memories is such that error conditions are not always consistent but frequently occur only under unique circumstances. In mass produced memory circuits, certain ones of the memory elements will have greater resistance to error conditions while others will be more prone to the generation of errors.
Large scale integration techniques have brought about the construction of large arrays of binary storage elements on a single chip of silicon. Such techniques and mass production of memory circuits have brought about high packing densities of such semiconductor memories. With this increase in packing density, the susceptibility to manufacturing defects and error conditions also increases. In order to improve the yield in the manufacturing process of semiconductor memories, redundant circuit elements have been fabricated, together with the normal circuit elements on a single chip. The redundant elements can then be substituted for defective circuit elements. In this manner, the entire semiconductor memory need not be scrapped, since defective portions can be easily replaced with redundant circuit elements. The advantages of the use of redundant circuit elements include increased fabrication yield as well as lower production costs.
One of the problems encountered in using redundant circuit elements is that the topology of the semiconductor memory array is changed by the implementation of redundancy. The topological change introduces difficulty in testing the semiconductor memory for pattern sensitivity. It is frequently the case that a particular erroneous data output produced by a semiconductor memory is caused by the pattern of data elements stored in the vicinity of the cell which produced the erroneous data output. This condition is primarily due to the extremely small sizes of the memory elements and numerous interconnecting signal lines which tend to produce parasitic capacitances. Due to the vast number of data combinations possible with even a moderate sized memory, it is readily apparent that comprehensive pattern sensitivity testing is necessary.
In the testing of semiconductor memories, the determination of weak cells can be performed by a simple exercising of the memory array, such as by writing all ones into the array and reading back all ones. However, some failure modes are not detectable until a more complex addressing scheme is applied to the memory. Such schemes have been developed which include bouncing from a cell to all four of its adjacent cells and stepping through the array such as by writing the subject cell to a zero, writing the four adjacent cells to a one, and then reading the subject cell to determine if it has been disturbed.
Numerous standard test patterns have been developed for bouncing between certain address locations in order to try to cause a disturbed condition to detect weak cells. An important aspect of such test patterns is the knowledge of the exact physical location of each of the cells being addressed. With the use of redundant elements substituted for defective circuit elements, this knowledge of the exact physical location of the cell being addressed is normally lost. When substitution of a redundant row or column into the memory array is made, it is no longer possible to know which memory cells are located next to each other, such as adjacent rows or adjacent columns, since any one of the columns or any one of the rows could have been defective and substituted for by a redundant element. Therefore, pattern testing in semiconductor memories utilizing redundant elements normally does not fully test the memories for weak cells.
A need has thus arisen for an identification circuit for identifying the location of a redundant element which has been substituted for an original defective element in a semiconductor memory. Such an identification circuit will permit true topological testing since the exact physical location of each of the cells, whether an original cell or a redundant element, will be known.